1. Technical Field
The present invention relates to memory devices in general, and in particular to chalcogenide memory devices. Still more particularly, the present invention relates to a method for manufacturing sidewall contacts for a chalcogenide memory device.
2. Description of the Prior Art
The use of phase change materials that can be electrically switched between a generally amorphous first structural state and a generally crystalline second structural state for electronic memory applications is well-known in the art. Phase change materials may also be electrically switched between different detectable states of local order across the entire spectrum between the completely amorphous and the completely crystalline states.
Some phase change materials exhibit different electrical characteristics according to their state. For example, chalcogenide materials exhibit a lower electrical conductivity in its amorphous state than it does in its crystalline state. The chalcogenide materials for making memory cells are typically compounds containing one or more elements selected from the group of tellurium, selenium, antimony, and germanium. Such chalcogenide materials can be switched between numerous electrically detectable conditions of varying resistivity in nanosecond time periods by using picojoules of energy. The resulting memory cell is truly non-volatile and will maintain the integrity of the stored information without the need for periodic signal refresh.
The operation of chalcogenide memory cells requires that a region of the chalcogenide memory material, called the chalcogenide active region, be subjected to a current pulse with a current density typically between 105 and 106 amperes/cm2. Such current density may be accomplished by making a small pore or opening in a dielectric material that is itself deposited onto a bottom electrode material. The chalcogenide material is then deposited over the dielectric material and into the pore to contact with the bottom electrode material. A top electrode material is then deposited over the chalcogenide material. Carbon is a commonly used electrode material although other materials, such as molybdenum and titanium nitride, have also been used.
The size of the chalcogenide active region is primarily defined by the volume of chalcogenide material that is contained within the pore delineated by the opening in the dielectric material. The upper portion of the chalcogenide material not contained within the pore acts as an electrode that in turn contacts with the top electrode material. The chalcogenide active region makes contact with the bottom electrode at an interface area that is substantially equal to the cross sectional area of the pore. As a result of such configuration, the interface area of the chalcogenide material within the chalcogenide active region is subjected to the high current density required for the operation of the chalcogenide memory cell. This is an undesirable situation because the high current density at the interface area of the chalcogenide active region with the bottom electrode causes mixing of the bottom electrode material with the chalcogenide material of the chalcogenide active region due to heating and electrophoretic effects. More specifically, the mixing of the electrode material with the chalcogenide material in the chalcogenide active region causes instability of the chalcogenide memory cell during operation.
Furthermore, with current semiconductor processing technology, the minimum achievable dimension of a contact for a chalcogenide memory device is limited by lithography tools. The size of a contact, which is determined by the diameter of the pore, varies with the square of photolithography feature size error and also with the square of the variability in etch bias. Thus, step coverage also becomes an issue because aspect ratio in the pore increases as the pore diameter decreases. This leads to reduced yield, reduced reliability and reduced cycling endurance. Consequently, it is desirable to provide an improve method for manufacturing contacts for a chalcogenide memory device.
In accordance with a preferred embodiment of the present invention, a first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.